The semiconductor device industry is continually driven to improve performance (e.g., faster chip speeds) and lower manufacturing costs. With a decrease in the feature size, the RC interconnect delay of an IC increases non-linearly and is generally much larger than the delay in switching the transistors (i.e., the gate delay). To counter the adverse effects of the RC delay and reduce manufacturing costs, new design techniques with higher levels of sophistication, new materials, and new interconnect manufacturing techniques have been introduced. A conventional interconnect design scheme is multilevel metallization, which span several planes and are isolated from one another by dielectric layers. To further reduce the RC delay, processes are moving towards dielectrics that have a dielectric constant lower than that of silica (k=3.9 to 4.0), generally referred to as low-k dielectrics. One class of low-k dielectrics is ultra low-k (ULK) dielectrics, generally defined herein as having a k value <2.7, such as porous carbon doped oxide, porous polymeric and certain silica based materials. Such ULK materials are known to be quite fragile and subject to scratching.
Low-k and ULK materials are typically much softer than traditional silica based dielectrics. As the dielectric constant is lowered, both the hardness and Young's modulus decrease significantly. When abrasives such as silica and alumina are used in CMP processes, they tend to scratch the soft surface, creating defects which can ultimately cause electrical shorts. Traditional CMP processes also introduce high frictional and shear forces on the surface. The poor adhesion of low-k films may also lead to delamination under conventional CMP conditions.
In the past decade, CMP has emerged as the fastest growing operation in the semiconductor manufacturing industry, and is expected to show fast growth in the future due to the introduction of copper/low dielectric constant (low-k and ULK) interconnects. An ideal CMP process should provide low defectivity, high planarity and a large, robust processing window. In the near future, CMP technology is expected to encounter two very significant hurdles related to scale-up from the current 300 mm wafer size to a 450 mm wafer size that is expected to occur and integration of fragile materials such as ULK dielectrics. Of all semiconductor processes (e.g., film deposition, thermal treatment etc.), the planarization technology is perhaps the most ill-equipped to make the transition to larger wafers. This is due to the extremely large number of processing variables (typically >20) that affect the uniformity across the wafers and defectivity obtained from the polishing process. Even the use of sophisticated sensing and control technologies may not be able to overcome the inherent fundamental deficiencies of conventional CMP processes described below.
Conventional CMP processes can be characterized as providing an “analog” response. The removal rate is dependent on a large number of process variables. The fundamental equation describing material removal is based on Preston's Law which states that the removal rate (RR) is directly proportional to applied pressure (P) and relative velocity (V) of slurry particles across the wafer surface.RR=Kp(PV)  (1)where, Kp is the Preston's constant. Although from the above equation it appears that there are only two variables, in actual practice there are more than 20 significant process variables, such as variables related to the slurry chemistry, substrate characteristics (e.g., edge effects and wafer bow), tool variables (e.g., pressure, linear velocity and vibration) and pad characteristics (e.g., mechanical properties, topology, and slurry/effluent transport). These variables are expected to be amplified for larger wafers (e.g. 400 to 450 mm wafers), making engineering solutions even more challenging.
Moreover, there are fundamental limitations in achieving high planarity patterned structures. In conventional CMP processes, significant deviation in planarity occurs when two dissimilar materials (e.g. Cu/low-k dielectrics) are simultaneously polished. Due to differences in rate of polishing of the metal and the dielectric, two common non-planarity defects occur, termed dishing and erosion. The large variations in local polishing rates due to pattern effects and polishing rate selectivity between metal and dielectric makes it difficult to minimize dishing and erosion. Furthermore, the large range of these non-planarities substantially decreases the process window for robust manufacturing. Such issues are expected to be amplified when larger wafers are polished. Thus the inherent “analog” characteristics of the CMP process may place fundamental limitation to the local planarity that can be achieved in a manufacturing environment.